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ISO-CMOS MT8809 8 x 8 Analog Switch Array
Features
* * * * * * * * * * Internal control latches and address decoder Short setup and hold times Wide operating voltage: 4.5V to 13.2V 12Vpp analog signal capability R ON 65 max. @ V DD=12V, 25C R ON 10 @ V DD=12V, 25C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Low power consumption ISO-CMOS technology Internal pull-up resistor for RESET pin
ISSUE 2
November 1988
Ordering Information MT8809AC 28 Pin Ceramic DIP MT8809AE 28 Pin Plastic DIP MT8809AP 28 Pin PLCC -40 to 85C
Description
The Mitel MT8809 is fabricated in MITEL's ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 8 array of crosspoint switches along with a 6 to 64 line decoder and latch circuits. Any one of the 64 switches can be addressed by selecting the appropriate six address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion.
Applications
* * * * * * Key systems PBX systems Mobile radio Test equipment /instrumentation Analog/digital multiplexers Audio/Video switching
CS
STROBE
DATA RESET
VDD
VSS
1 AX0
1 ****************
AX1 AX2 AY0 AY1 AY2 64 64
8x8 6 to 64 Decoder Latches Switch Array
Xi I/O (i=0-7)
*******************
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
3-21
MT8809
ISO-CMOS
AY2 STROBE CS DATA VSS X0 X2 X4 X6 RESET Y7 Y6 Y5 Y4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AY1 AY0 AX2 AX1 AX0 X1 X3 X5 X7 VDD Y0 Y1 Y2 Y3
4 3 2 1 28 27 26
*
DATA CS STROBE AY2 AY1 AY0 AX2
28 PIN CERDIP/PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 Name AY2 AY2 Address Line (Input). Description
STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes low and DATA must be stable on the rising edge of STROBE. Active Low. CS DATA VSS X0, X2, X4, X6 RESET Chip Select (Input): this is used to select the device. Active Low. DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. Ground Reference. X0, X2, X4 and X6 Analog (Inputs/Outputs): these are connected to the X0, X2, X4 and X6 rows of the switch array. Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. A 100k internal pull-up resistor is also provided. This can be used in conjunction with a 0.1F capacitor (connected to the RESET pin) to perform power-on reset of the device. Active Low. Y7 - Y0 Analog (Inputs/Outputs): these are connected to the Y0 - Y7 columns of the switch array. Positive Power Supply. X7, X5, X3 and X1 Analog (Inputs/Outputs): these are connected to the X7, X5, X3 and X1 rows of the switch array.
3 4 5 6-9 10
11-18 19 20-23 24-26 27, 28
Y7 - Y0 VDD X7, X5, X3, X1
AX0-AX2 AX0 - AX2 Address Lines (Inputs). AY0, AY1 AY0 and AY1 Address Lines (Inputs).
3-22
Y6 Y5 Y4 Y3 Y2 Y1 Y0
12 13 14 15 16 17 18
VSS X0 X2 X4 X6 RESET Y7
5 6 7 8 9 10 11
25 24 23 22 21 20 19
AX1 AX0 X1 X3 X5 X7 VDD
28 PIN PLCC
ISO-CMOS
Functional Description
The MT8809 is an analog switch matrix with an array size of 8 x 8. The switch array is arranged such that there are 8 columns by 8 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 64 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0-AX2). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs are low and are latched on the rising edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. A logical "0" on the RESET input will asynchronously return all memory locations to logical "0" turning off all crosspoint switches regardless of whether CS is high or low.
MT8809
Address Decode
The six address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be high and CS must go low while the address and data are set up. Then the STROBE input is set low and then high causing the data to be latched. The data can be changed while STROBE is low, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the rising edge of STROBE in order for correct data to be written to the latch.
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MT8809
ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.
Parameter 1 2 3 4 5 6 Supply Voltage Analog Input Voltage Digital Input Voltage Current on any I/O Pin Storage Temperature Package Power Dissipation PLASTIC DIP CERDIP Symbol VDD VSS VINA VIN I TS PD PD -65 Min -0.3 -0.3 -0.3 VSS-0.3 Max 15.0 VDD+0.3 VDD+0.3 VDD+0.3 15 +150 0.6 1.0 Units V V V V mA C W W
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated.
Characteristics 1 2 3 4 Operating Temperature Supply Voltage Analog Input Voltage Digital Input Voltage Sym TO VDD VINA VIN Min -40 4.5 VSS VSS Typ 25 Max 85 13.2 VDD VDD Units C V V V Test Conditions
DC Electrical CharacteristicsCharacteristics 1 Quiescent Supply Current
Voltages are with respect to VSS=0V, VDD =12V unless otherwise stated.
Sym IDD
Min
Typ 1 120 0.5 5
Max 100 400 1.6 15 500 0.8
Units A A mA mA nA V V A
Test Conditions All digital inputs at VIN=VSS VDD except RESET = VDD. All digital inputs at VIN=VSS or VDD except RESET = VSS. All digital inputs at VIN=2.4V, VDD=5.0V All digital inputs at VIN=3.4V IVXi - VYjI = VDD - VSS See Appendix, Fig. A.1
2 3 4 6
Off-state Leakage Current (See G.9 in Appendix) Input Logic "0" level Input Logic "1" level Input Leakage (digital pins)
IOFF VIL VIH ILEAK 3.0
1
0.1
10
All digital inputs at VIN = VSS or VDD; RESET = VDD
DC Electrical Characteristics are over recommended temperature range. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics Sym 25C Typ 1 On-state VDD=12V Resistance VDD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) 2 Difference in on-state resistance between two switches (See G.4 in Appendix)
3-24
70C Typ Max 75 85 215
85C Typ Max 80 90 225
Units
Test Conditions
Max 65 75 185
RON
45 55 120

VSS=0V,VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2
RON
5
10
10
10
VDD=12V, VSS=0, VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2
ISO-CMOS
MT8809
AC Electrical Characteristics - Crosspoint Performance- VDC is the external DC offset at the analog I/O pins.
Voltages are with respect to VDD =5V, VDC =0V, VSS=-7V, unless otherwise stated.
Characteristics 1 2 3 Switch I/O Capacitance Feedthrough Capacitance Frequency Response Channel "ON" 20LOG(VOUT/VXi)=-3dB Total Harmonic Distortion (See G.5, G.6 in Appendix) Feedthrough Channel "OFF" Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix).
Sym CS CF F3dB
Min
Typ 20 0.2 45
Max
Units pF pF MHz
Test Conditions f=1 MHz f=1 MHz Switch is "ON"; VINA = 2Vpp sinewave; RL = 1k See Appendix, Fig. A.3 Switch is "ON"; VINA = 2Vpp sinewave f= 1kHz; RL=1k All Switches "OFF"; VINA= 2Vpp sinewave f= 1kHz; RL= 1k. See Appendix, Fig. A.4 VINA=2Vpp sinewave f= 10MHz; RL = 75. VINA=2Vpp sinewave f= 10kHz; RL = 600. VINA=2Vpp sinewave f= 10kHz; RL = 1k. VINA=2Vpp sinewave f= 1kHz; RL = 10k. Refer to Appendix, Fig. A.5 for test circuit. RL=1k; CL=50pF
4 5
THD FDT
0.01 -95
% dB
6
Xtalk
-45 -90 -85 -80
dB dB dB dB
7
Propagation delay through switch
tPS
30
ns
Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
AC Electrical Characteristics - Control and I/O Timings- VDC is the external DC offset applied at the analog
I/O pins. Voltages are with respect to VDD=5V, VDC=0V , VSS=-7V, unless otherwise stated.
Characteristics 1 Control Input crosstalk to switch (for CS, DATA, STROBE, Address) Digital Input Capacitance Switching Frequency Setup Time DATA to STROBE Hold Time DATA to STROBE Setup Time Address to STROBE Hold Time Address to STROBE Setup Time CS to STROBE Hold Time CS to STROBE STROBE Pulse Width RESET Pulse Width STROBE to Switch Status Delay DATA to Switch Status Delay RESET to Switch Status Delay
Sym CXtalk
Min
Typ 30
Max
Units mVpp
Test Conditions VIN=3V+VDC squarewave; RIN=1k, RL=1k. See Appendix, Fig. A.6 f=1MHz RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF
2 3 4 5 6 7 8 9 10 11 12 13 14
CDI FO tDS tDH tAS tAH tCSS tCSH tSPW tRPW tS tD tR 10 10 10 10 10 10 20 40
10 20
pF MHz ns ns ns ns ns ns ns ns
40 50 35
100 100 100
ns ns ns
Q Q Q Q Q Q Q Q Q Q Q
Q
Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Refer to Appendix, Fig. A.7 for test circuit. 3-25
MT8809
ISO-CMOS
tCSS tCSH 50% tRPW
CS
50%
RESET STROBE
50%
tSPW 50% 50%
50%
50%
ADDRESS
50% tAS
50% tAH 50% tDS tDH 50%
DATA
ON
SWITCH*
OFF tD tS tR tR
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AY2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AY1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AY0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
AX2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
AX1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
AX0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Connection
X0 X1 X2 X3 X4 X5 X6 X7 X0 X1 X2 X3 X4 X5 X6 X7 X0 X1 X2 X3 X4 X5 X6 X7 X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3
AY2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AY1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AY0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
AX2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
AX1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
AX0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Connection
X0 X1 X2 X3 X4 X5 X6 X7 X0 X1 X2 X3 X4 X5 X6 X7 X0 X1 X2 X3 X4 X5 X6 X7 X0 X1 X2 X3 X4 X5 X6 X7 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7
Table 1. Address Decode Truth Table
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